# NVIDIA Developer Blog
> Technology company that designs powerful computer chips used for video games, data centers, and artificial intelligence.

## Articles

### [Streamlining Resource Binding with End-to-End Support for Vulkan Descriptor Heaps](https://yomu.fyi/post/streamlining-resource-binding-with-end-to-end-support-for-vulkan-descr.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Tanya Lenz
- Published: Jun 25, 2026

Vulkan introduces the VK\_EXT\_descriptor\_heap extension to refactor GPU resource binding, replacing set-based layouts and pool allocations with application-managed descriptor memory heaps. This approach aligns Vulkan closer to Direct3D 12 and benefits workloads like dynamic texture indexing and complex ray tracing shaders. Developers manage memory directly, binding a single resource heap and a separate sampler heap globally to avoid high rebinding overhead. Shaders can access descriptors either through mapping structures using constant offsets or push constants, or directly via untyped pointers enabled by VK\_KHR\_shader\_untyped\_pointers. Support is integrated into NVIDIA drivers 610, Vulkan Headers 1.4.340, and Nsight Graphics 2026.2 for frame capture and inspection.


### [Q&A: How KRAFTON Built PUBG Ally, a Co-Playable Character Powered by NVIDIA ACE](https://yomu.fyi/post/q-a-how-krafton-built-pubg-ally-a-co-playable-character-powered-by-nvi.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Elizabeth Goodman
- Published: Jun 25, 2026

KRAFTON developed PUBG Ally, an on-device AI co-playable character for PUBG: BATTLEGROUNDS, using NVIDIA ACE tooling and models. Conventional non-playable characters rely on fixed dialogue, but PUBG Ally processes live game states and player voice input in real time. The interactive pipeline combines automatic speech recognition, a quantized Mistral-NeMo-Minitron-2B small language model, and a custom text-to-speech model running locally on client GPUs with at least 8GB of VRAM. To minimize latency, the architecture separates reactive gameplay into a behavior-tree System 1 layer while routing strategic decisions and speech generation to the language model. KRAFTON tuned the non-deterministic system across multi-layer evaluations and large-scale playtests with over a thousand players.


### [Accelerating BEV Pooling on NVIDIA GPUs for Physical AI Applications](https://yomu.fyi/post/accelerating-bev-pooling-on-nvidia-gpus-for-physical-ai-applications.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: John Yang
- Published: Jun 24, 2026

Bird's-eye-view (BEV) pooling frequently becomes an inference latency bottleneck in spatial AI pipelines due to irregular memory access patterns and scatter-reduce operations. BEVPoolV3 addresses this by tailoring kernel execution to the GPU memory regime, specifically distinguishing between DRAM-bound and L2-cache-resident working sets. The implementation reduces redundant scatter traffic via depth-outer traversal, precomputes indices to eliminate runtime integer division, minimizes duplicate depth loads, and adopts interval-owned writes to bypass atomic operations. On a canonical 49 MB nuScenes working set, BEVPoolV3 accelerates TensorRT plugin execution from 274.0 µs down to 16.4 µs on an NVIDIA RTX PRO 6000 Blackwell Max-Q GPU. Furthermore, profiling with Nsight Compute reveals that L2-resident scatter-reduce operators achieve optimal efficiency with FP8, avoiding the ALU instruction overhead of NVFP4 decoding.


### [Maximize AI Factory Energy Efficiency Through Full-Stack Inference and Training Optimizations](https://yomu.fyi/post/maximize-ai-factory-energy-efficiency-through-full-stack-inference-and.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Sachin Idgunji
- Published: Jun 23, 2026

Power costs comprise up to 40% of AI factory operating expenses, making performance per watt critical within fixed site power limits. Operators maximize throughput by combining architectural enhancements, narrow-precision formats like NVFP4, and mixture-of-experts model designs that activate fewer parameters per token. During distributed LLM training in Megatron-LM, tuning individual GPU speeds along critical execution paths eliminates idle power waste without extending total training time. Additionally, the NVIDIA DSX platform orchestrates dynamic power allocation, 45°C direct-to-chip liquid cooling, and grid integration across racks and facilities. Together, these full-stack optimizations enable performance-optimized AI factories to deliver up to 2.6 times more tokens per second per megawatt.


### [Boost Inference Performance up to 15x on NVIDIA Blackwell Using DFlash Speculative Decoding](https://yomu.fyi/post/boost-inference-performance-up-to-15x-on-nvidia-blackwell-using-dflash.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Amr Elmeleegy
- Published: Jun 23, 2026

Sequential token generation in autoregressive LLMs limits GPU utilization and serving throughput, while conventional speculative decoding remains constrained by autoregressive draft models. DFlash addresses this bottleneck by employing a lightweight block-diffusion drafter that predicts an entire block of masked candidate tokens in a single forward pass. The architecture incorporates target hidden-state conditioning and key-value injection into draft model projections while relying on the target model for parallel verification. Evaluated on NVIDIA Blackwell GPUs across TensorRT-LLM, vLLM, and SGLang, DFlash increases gpt-oss-120b throughput by more than 15x at high interactivity targets and delivers up to 5.8x speedups on Gemma 4 31B compared to autoregressive decoding.


### [Build an AI Scientist for Life Science Discovery with NVIDIA BioNeMo Agent Toolkit](https://yomu.fyi/post/build-an-ai-scientist-for-life-science-discovery-with-nvidia-bionemo-a.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Kyle Tretina
- Published: Jun 23, 2026

General-purpose AI agents often struggle with biomolecular discovery because scientific workflows require precise model selection, strict input formatting, and artifact interpretation. The NVIDIA BioNeMo Agent Toolkit bridges this gap by providing BioNeMo Skills and Model Context Protocol wrappers on top of accelerated NVIDIA NIM microservices. These skills instruct agents on tool capabilities, required inputs, expected file formats like CIF and SMILES, and specific failure modes. Developers can route requests through hosted endpoints for testing or deploy local NIM microservices on GPU nodes to lower warm per-call latency during iterative candidate generation loops. Internal benchmarks using Codex CLI demonstrate that equipping agents with BioNeMo Skills improves task completion rates from 57.1% to 100% while doubling token efficiency across passing assertions.


### [How Telcos Build Autonomous Networks with Agentic AI](https://yomu.fyi/post/how-telcos-build-autonomous-networks-with-agentic-ai.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Amogh Dendukuri
- Published: Jun 23, 2026

Telecom operators currently operate mostly within Levels 2 and 3 of the TM Forum autonomous networks taxonomy, relying on predefined scripts. Progressing to Levels 4 and 5 demands autonomous systems capable of intent comprehension, real-time telemetry sensing, and cross-domain action coordination. To address this, an autonomy platform architecture combines domain-specific reasoning models, agent harnesses, and isolated sandboxed runtimes. Workflows separate responsibilities among on-demand agents, long-running execution loops, and deep-research multi-agent systems that evaluate ranked remediation paths or design wireless algorithms. Initial experiments in simulated SR-MPLS routing and wireless physical or MAC layer design show autonomous discovery can deliver measurable gains over standard operational and engineering baselines.


### [CCCL Runtime: A Modern C++ Runtime for CUDA](https://yomu.fyi/post/cccl-runtime-a-modern-c-runtime-for-cuda.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Piotr Ciolkosz
- Published: Jun 22, 2026

NVIDIA CCCL runtime introduces modern C++ abstractions for fundamental CUDA programming concepts starting in CUDA Toolkit 13.2 and CCCL 3.2. Designed as an alternative to the traditional CUDA runtime API, the library eliminates implicit global state by requiring explicit dependencies, such as binding streams directly to specific device references. The API enforces strong typing through owning types and non-owning reference types, omits default stream usage to ensure all streams remain non-blocking, and handles errors via standard C++ exceptions. In addition, CCCL runtime simplifies kernel launches through kernel functors that enable automatic template argument deduction and automatically transforms owning buffer arguments into device spans.


### [Enable Real-Time AI for High-Speed Data Acquisition with DAQIRI](https://yomu.fyi/post/enable-real-time-ai-for-high-speed-data-acquisition-with-daqiri.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Cara Laasch
- Published: Jun 22, 2026

Scientific instruments and high-bandwidth sensors generate immense data volumes, but traditional architectures rely on a store-then-analyze model that bottlenecks real-time discovery and forces extensive data discarding. NVIDIA DAQIRI shifts data acquisition to a software-centric pipeline that connects streaming detectors directly to GPU computing. Built as part of the NVIDIA Holoscan Platform, DAQIRI uses DPDK to bypass the Linux kernel and move UDP and RoCE v2 traffic directly from the NIC into GPU DMA buffers at line rates exceeding hundreds of gigabits per second. The system automates packet reordering, flow steering, and on-GPU data conversions such as mapping wire int4 payloads into fp16 tensors using YAML configuration files and simple C++ or Python APIs. This enables real-time edge processing, filtering, and model inference across experimental pipelines like CERN ATLAS.


### [Inside NVIDIA Halos for Robotics: A Full-Stack Functional Safety System for Physical AI](https://yomu.fyi/post/inside-nvidia-halos-for-robotics-a-full-stack-functional-safety-system.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Suhas Hariharapura Sheshadri
- Published: Jun 22, 2026

NVIDIA announced the launch of NVIDIA Halos for Robotics, a full-stack functional safety system designed for industrial robots, humanoids, and autonomous mobile robots. The platform extends NVIDIA's functional safety architecture from autonomous vehicles into robotics, utilizing NVIDIA IGX Thor and the NVIDIA Holoscan Sensor Bridge as its hardware foundation. On top of this hardware, Halos OS provides the base Halos Core safety operating system and application blueprints, including an Outside-In Safety Blueprint that leverages external worksite cameras and safety decision modules. Platform hardware safety features include an isolated IEC 61508 SIL 3 capable Safety Island alongside extensive fault-detection mechanisms. To accelerate compliance, the accredited NVIDIA Halos AI Systems Inspection Lab assesses partner integrations before final third-party certification.


### [Building AI Agents for AR Glasses and XR Devices with NVIDIA XR AI](https://yomu.fyi/post/building-ai-agents-for-ar-glasses-and-xr-devices-with-nvidia-xr-ai.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Greg Barbone
- Published: Jun 16, 2026

Building AI experiences for augmented reality and wearable devices requires bridging hardware with live media streams, multimodal models, enterprise tools, and runtime infrastructure. NVIDIA XR AI provides an open-source, modular framework connecting extended reality headsets and smart glasses to GPU-accelerated services across cloud, edge, and workstations. In this architecture, camera frames and microphone audio ingest into an XR Media Hub that routes data while keeping raw video pixels in shared memory to minimize overhead. The ecosystem uses NVIDIA Cosmos models for vision-language grounding, NVIDIA Nemotron models for reasoning and tool invocation, and the Model Context Protocol for enterprise integrations. Optional agent orchestration via NVIDIA NeMo Agent Toolkit and spatial streaming through NVIDIA CloudXR support complex workflows across healthcare and manufacturing.


### [Build Your Own Transaction Foundation Model for Financial Intelligence](https://yomu.fyi/post/build-your-own-transaction-foundation-model-for-financial-intelligence.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Benjamin Wu
- Published: Jun 16, 2026

Production financial intelligence systems frequently rely on hand-engineered tabular features and rule sets that are brittle, expensive to maintain, and blind to historical sequential patterns. NVIDIA demonstrates an accelerated reference pipeline that replaces standard BPE tokenization with a GPU-based domain tokenizer, converting raw transactions into semantic tokens with an 8,192-token context window. Using the NeMo AutoModel library, a compact 29-million parameter decoder-only transformer is pretrained from scratch on unlabeled transaction sequences using causal language modeling. Learned sequence embeddings are extracted, compressed using PCA, and concatenated with raw tabular features to train a downstream GPU-accelerated XGBoost fraud detection model. On the IBM TabFormer benchmark dataset, this combined approach achieves a 41.76% lift in Average Precision over the baseline model relying solely on raw tabular features.


### [NVIDIA Blackwell Tops MLPerf Training 6.0 with Industry-Leading Scale and Performance](https://yomu.fyi/post/nvidia-blackwell-tops-mlperf-training-6-0-with-industry-leading-scale.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Farshad Ghodsian
- Published: Jun 16, 2026

NVIDIA submitted results across all MLPerf Training v6.0 benchmarks, setting performance records on workloads including the DeepSeek-V3 and GPT-OSS-20B Mixture of Experts models. To scale training up to 8,192 Blackwell GPUs, NVIDIA combined hardware cluster designs with scale-out networking via Spectrum-X Ethernet and Quantum InfiniBand. The engineering team eliminated CPU-GPU synchronization bottlenecks in token-dropless MoEs by implementing full-iteration CUDA graphs with synchronization-free operators and paged stashing. Further software optimizations included CuTe DSL kernel fusions, an MXFP8 attention block in the Transformer Engine, and transitioning router elementwise math to FP32. Across these benchmarks, the GB300 NVL72 platform achieved the fastest time to train at scale and the highest normalized per-accelerator performance.


### [Build On-Device AI Companions with the NVIDIA ACE Game Agent SDK and Unreal Engine 5 Plugins](https://yomu.fyi/post/build-on-device-ai-companions-with-the-nvidia-ace-game-agent-sdk-and-u.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Phillip Singh
- Published: Jun 16, 2026

Game developers integrating on-device artificial intelligence companions face challenges such as conversational latency, state synchronization, and loop prevention. NVIDIA announced the open-source ACE Game Agent SDK alongside a suite of Unreal Engine 5 plugins to streamline native, hardware-accelerated character pipelines. The SDK offers Agent, Chat, and RAG APIs, enabling characters to execute multi-step tool-assisted reasoning and query game databases. Unreal Engine 5 plugins introduce local runtime models including nemo-conformer-ctc-120m for speech recognition, Qwen 3.5 4B for language generation, and Chatterbox Turbo 350M for speech synthesis. Additional tooling expands to motion generation via Animotive Kimodo and rendering updates with the DLSS 4.5 Unreal Engine plugin.


### [How to Optimize Transformer-Based Models for Low-Precision Training](https://yomu.fyi/post/how-to-optimize-transformer-based-models-for-low-precision-training.md)
- Company: [NVIDIA Developer Blog](https://yomu.fyi/company/nvidia-developer-blog.md)
- Author: Jonathan Mitchell
- Published: Jun 16, 2026

Accelerating transformer training requires understanding how low-precision formats such as FP8 and NVFP4 impact specific general matrix multiplication (GEMM) workloads. Transformer configurations do not explicitly reveal these shapes, making microbenchmarks necessary before committing to full training runs. NVIDIA Transformer Engine enables quantization and kernel dispatch across precisions, which can be evaluated in realistic autocast mode or kernel-only prequantized mode. Profiling the ESM2-15B model on NVIDIA B300 GPUs demonstrated that NVFP4 achieved a 1.79x blended forward propagation speedup over MXFP8 and up to 4.01x over BF16 in prequantized execution. Although large GEMM dimensions successfully overcome quantization overheads, dynamic scaling, Hadamard transforms, and kernel selection asymmetries moderate real-world gains.


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