# MTIA 300: Meta’s First Training Chip with Built-in NICs and Communication-Offloading Engines

[Meta](https://yomu.fyi/company/meta) · By Rajiv Krishnamurthy, Wes Bland · Aug 24, 2026

## Summary

Training recommendation models poses distinct network bottlenecks because massive embedding tables trigger frequent collective operations that compete with computation on standard GPUs. Meta designed the MTIA 300 accelerator to overcome this by embedding two network chiplets containing twelve 800 Gbps RDMA NICs directly inside the chip package. The architecture offloads communication from its compute grid to sixteen dedicated message engines equipped with RISC-V cores and near-memory compute reduction blocks. Working alongside the co-designed HCCL library, the chip autonomously compiles and executes collective communication subgraphs without host CPU intervention. On a 150-billion-parameter production recommendation model, MTIA 300 delivered communication speeds 3.9 times faster than an equivalent GPU cluster while keeping concurrent compute degradation under 0.5 percent.

## Takeaways

- MTIA 300 integrates twelve custom 800 Gbps RDMA NICs directly on the chip package to provide 1.2 TB/s of total I/O bandwidth without traversing a PCIe bus.
- Sixteen message engines with near-memory compute blocks deliver over 2.8 TB/s of reduction throughput, reducing compute degradation during concurrent GEMM and collective operations to less than 0.5%.
- The co-designed HCCL communication library compiles collectives into subgraphs for autonomous execution on the device, eliminating host CPU mediation after instructions reach high-bandwidth memory.

**Tags:** [Architecture](https://yomu.fyi/topic/architecture), [Machine Learning](https://yomu.fyi/topic/machine-learning), [Performance](https://yomu.fyi/topic/performance), [Recommendation Systems](https://yomu.fyi/topic/recommendation-systems), [Scalability](https://yomu.fyi/topic/scalability)

[Read original post](https://engineering.fb.com/2026/08/24/networking-traffic/mtia-300-meta-training-chip-built-in-nics)