---
title: "NVIDIA NVLink Fusion Brings NVHBM to Next-Generation AI Infrastructure"
description: "AI factories need custom XPUs to handle larger models and complex reasoning workloads, but scaling them requires HBM bandwidth, package and silicon area, power efficiency, supply-chain resilience, and rack-scale integration. NVIDIA NVLink Fusion addresses this by connecting custom XPUs and CPUs to NVIDIA’s AI infrastructure platform, using its scale-up and scale-out stack, ecosystem, and MGX rack-scale architecture. Its package-level NVHBM custom HBM base die, designed and validated with leading memory vendors, provides up to 30% more bandwidth and 15% lower HBM power usage than standard HBM4e, while enabling up to 25% more compute die area. The combined NVLink Fusion and NVHBM design is described as delivering a 30% overall end-to-end performance increase per XPU and simplifying integration into heterogeneous, rack-scale deployments."
---

# NVIDIA NVLink Fusion Brings NVHBM to Next-Generation AI Infrastructure

[NVIDIA](https://yomu.fyi/company/nvidia-developer-blog) · Farshad Ghodsian · Aug 26, 2026

**Type:** Announcement

## Summary

AI factories need custom XPUs to handle larger models and complex reasoning workloads, but scaling them requires HBM bandwidth, package and silicon area, power efficiency, supply-chain resilience, and rack-scale integration. NVIDIA NVLink Fusion addresses this by connecting custom XPUs and CPUs to NVIDIA’s AI infrastructure platform, using its scale-up and scale-out stack, ecosystem, and MGX rack-scale architecture. Its package-level NVHBM custom HBM base die, designed and validated with leading memory vendors, provides up to 30% more bandwidth and 15% lower HBM power usage than standard HBM4e, while enabling up to 25% more compute die area. The combined NVLink Fusion and NVHBM design is described as delivering a 30% overall end-to-end performance increase per XPU and simplifying integration into heterogeneous, rack-scale deployments.

## Context

AI accelerator programs must support larger models and increasingly complex training, inference, and agentic workloads. The source identifies HBM bandwidth, package and silicon area, power, thermal design, supply-chain resilience, and rack-scale deployment as constraints, while memory qualification, package integration, and validation can bottleneck custom accelerator development.

## Approach / What changed

NVLink Fusion connects custom XPUs and CPUs to NVIDIA’s AI infrastructure platform through the NVLink Fusion chiplet and provides access to NVIDIA scale-up and scale-out technologies, its ecosystem, and MGX rack-scale architecture. NVHBM complements this at the package level with a custom HBM base die, a redesigned physical memory interface, a memory controller integrated into the 3D HBM stack, and a custom PHY validated with leading memory vendors.

## Takeaways

- NVHBM provides up to 30% more memory bandwidth per stack and up to 15% lower HBM power usage than standard HBM4e, targeting bandwidth-intensive training and inference workloads.
- NVHBM reduces PHY and support area by up to 67% and can provide up to 25% more compute die area; the source also reports up to 80% more usable silicon across the layout.
- The NVLink Fusion chiplet connects custom XPUs across a rack-scale NVLink domain, supporting distributed compute, expert parallelism, synchronized caches, and integration with GPUs for heterogeneous compute.

**Tags:** [Architecture](https://yomu.fyi/topic/architecture), [Performance](https://yomu.fyi/topic/performance), [Scalability](https://yomu.fyi/topic/scalability)

- Source: [NVIDIA](https://developer.nvidia.com/blog/nvidia-nvlink-fusion-brings-nvhbm-to-next-generation-ai-infrastructure)
- Source URL: https://developer.nvidia.com/blog/nvidia-nvlink-fusion-brings-nvhbm-to-next-generation-ai-infrastructure
- Ingested by Yomu: 2026-08-29T01:39:22.266Z

[Read original post](https://developer.nvidia.com/blog/nvidia-nvlink-fusion-brings-nvhbm-to-next-generation-ai-infrastructure)