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Scaling up BERT-like model Inference on modern CPU - Part 2
Ella Charlaix, Jeff Boudier, Morgan Funtowicz, Michael Benayoun
Summary
Scaling transformer inference on modern CPUs requires coordinating hardware capabilities with software optimizations across memory allocation, parallel execution, and mathematical kernel libraries. Intel Ice Lake Xeon processors deliver up to seventy-five percent faster inference across natural language processing tasks compared to Cascade Lake by combining Sunny Cove architecture improvements with dedicated extensions like Intel Extension for PyTorch. Fine-tuning software knobs such as alternative allocators, threading runtimes like Intel OpenMP, and core allocations can involve thousands of possible configuration combinations. Rather than evaluating these combinations through exhaustive brute force, Bayesian optimization via Intel SigOpt achieves comparable latency within roughly twenty trials and reveals experiment-dependent parameter importance. These software tuning strategies enable low-latency production transformer serving without dedicated accelerators.
Context
Maximizing deep learning inference efficiency on CPUs requires navigating complex software and hardware interactions, as standard setups often leave underlying multi-core architectures and low-level instruction sets underutilized.
Approach / What changed
Evaluating Intel oneAPI software components including Intel OpenMP, oneDNN, and framework extensions alongside memory allocators such as jemalloc, mimalloc, or tcmalloc, while utilizing Intel SigOpt Bayesian optimization to tune configuration parameters across sequence lengths and core counts.
Takeaways
- Intel Ice Lake Xeon processors achieve up to 75% faster inference on natural language processing tasks compared to Cascade Lake processors due to Sunny Cove architecture features and software enhancements.
- Intel oneAPI provides domain-specific libraries such as Intel oneDNN for neural network primitives, Intel oneMKL for linear algebra, and Intel OpenMP for high-performance multi-core parallelization.
- Using Intel SigOpt for Bayesian optimization allows tuning parameter spaces with up to 1,920 configurations in roughly 20 to 25 trials while keeping latency within 8.6% of brute-force search results.
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