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Systems Engineering Playbook: Optimizing Qwen 3.5-397B MoE on Ironwood (TPU7x)
Summary
Serving Qwen3.5-397B, a 397-billion-parameter sparse Mixture-of-Experts model, on Ironwood (TPU v7x) requires fitting roughly 400 GB of weights into HBM while sustaining utilization across contrasting workloads. The report applies a modular, model-agnostic playbook built from reusable JAX/Pallas kernels and hardware-aware cost models, focusing new work on Gated DeltaNet linear attention and Attention Data Parallelism while integrating changes into vLLM and SGLang. The architecture activates exactly 17 billion parameters per token and combines 15 repeating blocks of three GDN layers and one GQA layer. Benchmarks use a single host with four Ironwood chips, eight logical devices, 8K/1K prefill-heavy and 1K/8K decode-heavy workloads, and concurrency tiers from 64 to 512. Between April and June 2026, stated optimizations improved inference performance by approximately 4.7x for 512-concurrency prefill-heavy workloads and 3.1x for decode-heavy workloads.
Context
Serving Qwen3.5-397B on Ironwood presents the challenge of loading its roughly 400 GB weight footprint into HBM and maximizing hardware utilization across compute-bound prefill-heavy and memory-bound decode-heavy workloads. The report also addresses the need to optimize successive open-weights model families without treating each architecture as an isolated effort.
Approach / What changed
The work uses a modular, model-agnostic optimization strategy based on reusable JAX/Pallas kernels and hardware-aware cost models. It targets Qwen 3.5-specific components, including Gated DeltaNet linear attention and Attention Data Parallelism, while applying custom sharding and kernel optimizations and integrating the resulting changes into vLLM and SGLang.
Takeaways
Qwen3.5-397B has 397 billion total parameters but activates exactly 17 billion per token, routing through 512 experts with the top 10 selected and one shared expert path always executed.
The evaluation covers 8K-input/1K-output prefill-heavy and 1K-input/8K-output decode-heavy workloads at concurrency levels of 64, 128, 256, and 512 on eight logical Ironwood devices.
The numerical verification layer reports zero deviation between Pallas-lowered gating weights and the high-precision Float32 reference path while monitoring softmax ranges and expert load balance.
Source and freshness
- Source
- developers.googleblog.com
- Published
- Added to Yomu
Summaries are generated from the original by a language model. Check the original before relying on it.
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