GoogleBilly RutledgeAnnouncement
Edge AI is fragmented across hundreds of proprietary chip architectures and incompatible toolchains, forcing developers to repeatedly optimize models for each target. Google Research’s Coral NPU addresses this with an open hardware and software standard built on RISC-V, now reaching a complete 32-bit architecture. The architecture combines a scalar frontend, a RISC-V vector co-processor, and a Matrix Execution Unit that uses outer-product multiply-accumulate to achieve up to 1 TOPS at 10mW average inference power. The v1.0 IREE/MLIR compiler toolchain compiles models from JAX, PyTorch, and TensorFlow directly to Coral NPU instructions, enabling write-once deployment across diverse power envelopes. Commercial silicon from Synaptics, including the Astra SR200 MCU and Coralboard developer kits, shows how the standard unifies edge AI from milliwatt wearables to 1 TOPS boards.
Edge AI development is hindered by fragmentation across numerous proprietary chip architectures and incompatible toolchains, forcing ML developers to rewrite and requantize models for each target device.
Google Research’s Coral NPU provides an open hardware and software standard based on RISC-V. The complete 32-bit architecture includes a scalar core, RVV v1.0 vector co-processor, and a Matrix Execution Unit using outer-product MAC for 2D matrix operations, configurable up to 1 TOPS at 10mW. The v1.0 IREE/MLIR compiler toolchain supports JAX, PyTorch, and TensorFlow, lowering models to native Coral NPU instructions. Commercial silicon from Synaptics, such as the Astra SR200 series and Coralboard kits, implements the standard across power envelopes from milliwatts to 1 TOPS.
The Coral NPU Matrix Execution Unit uses a dedicated outer-product multiply-accumulate engine that computes 256 MACs per cycle, delivering quadratic throughput scaling for GEMM and GEMV operations common in modern ML workloads.
The v1.0 IREE/MLIR compiler toolchain takes models from JAX, PyTorch, or TensorFlow through StableHLO and TOSA, partitions workloads between host CPU and Coral NPU, and lowers directly to scalar, vector, and matrix instructions.
Synaptics Astra SR200 series integrates Coral NPU IP to deliver 400 GOPS in an ultra-low-power MCU package, while the Coralboard SL offers 1 TOPS for Linux-based IoT and robotics, both supported by the same open compiler.
The v1.0 IREE/MLIR compiler supports JAX, PyTorch, and TensorFlow models, processing them through StableHLO and TOSA representations before lowering to native Coral NPU instructions.
Yes, because the same architecture and compiler foundation are used across products. ML teams can optimize a model once and deploy it to milliwatt-class wearables like the Coralboard SR or a 1 TOPS board like the Coralboard SL using identical workflows.
Synaptics has launched the Astra SR200 series MCU (400 GOPS) and the Coralboard SL (1 TOPS) developer kit, available via DigiKey, with the new Coralboard SR also announced.
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