NVIDIA Vera CPU: Olympus Cores Built for Maximum Single-Thread Performance in Agentic AI

Summary

Agentic AI workloads shift critical execution paths onto CPUs through sandboxed environments that execute code, invoke tools, and manage runtime states. The NVIDIA Vera CPU addresses these compute requirements via Olympus cores built to maximize single-thread performance and instructions per cycle under full socket load. To handle irregular control flows and pointer-heavy structures, Olympus combines a ten-wide decode engine, neural branch prediction supporting two taken branches per cycle, dependency-breaking acceleration, and dedicated graph prefetchers. Across scale-up systems, dual-socket Vera configurations leverage second-generation NVLink-C2C interconnects to maintain a clean two-NUMA-node topology alongside PCIe 6.4, CXL 3.1, and Arm CCA confidential computing. These architectural choices provide predictable latency and memory bandwidth across highly concurrent reinforcement learning and agent loops.

Takeaways

1. 1

   Olympus features a 10-wide decode engine and a neural branch predictor supporting up to two taken branches per cycle to sustain throughput across branch-heavy agent runtimes.

2. 2

   The architecture incorporates memory renaming, value prediction, critical-path acceleration, and dedicated graph prefetching to mitigate stalls in serialized, pointer-heavy dependency chains.

3. 3

   Dual-socket Vera deployments use second-generation NVLink-C2C to present each socket as a single NUMA domain, avoiding chiplet-based memory fragmentation while exposing 176 PCIe lanes and CXL 3.1.