NVIDIAMichelle HortonBenchmark
Solving Agentic AI Fleet Challenges with NVIDIA Vera CPU
Summary
Agentic AI fleets must handle unpredictable trajectories in which long sequential reasoning chains are interrupted by short bursts of parallel tool calls, retrieval, sandbox, or sub-agent work. Telemetry from 163,594 sessions found over 97% had unique trajectory profiles, making fleet sizing around several specialized CPU designs impractical; the sequential path is latency-bound while fan-out requires concurrency. It presents NVIDIA Vera CPU as a single balanced design point, combining strong loaded per-core performance, concurrency, memory bandwidth, and a low-latency monolithic architecture, with Olympus cores using a wide front end, branch prediction, and deep out-of-order execution. Using estimated SPEC CPU® 2026 results across four agentic workloads, it reports up to 1.5x the agentic performance of AMD Venice, while noting that Venice figures were estimated from SPECrate® 2026 data and that results may vary.
Context
Agentic workloads have highly variable execution trajectories: over 97% of 163,594 sessions had unique profiles. Their long, sequential dependency chains are latency-bound, while intermittent fan-out creates bursts of concurrent tool calls, retrieval operations, sandboxes, or sub-agents. This variability makes it impractical to right-size a fleet around multiple specialized CPU design points.
Approach / What changed
The proposed approach is a single balanced CPU design point. NVIDIA Vera combines strong per-thread performance while the full CPU is active with enough concurrency for fan-out, ample memory bandwidth, efficient power use, and a low-latency monolithic architecture. Its Olympus cores use a wide front end, advanced branch prediction, deep out-of-order execution, and a high-bandwidth memory subsystem.
Takeaways
A real Claude Code session described in the source ran for 33 minutes, with the main agent following a long sequential trajectory and sub-agents producing brief bursts of parallel work.
Turning off cores to increase single-threaded performance can leave 8 GB per core unused and strand up to 1.5 TB of memory capacity.
AMD Venice workload figures were estimated from a SPECrate® 2026_int_base score of 2070, with components normalized using internal Turin measurements; the source says results may vary.
Source and freshness
- Source
- developer.nvidia.com
- Published
- Added to Yomu
- Last updated
Summaries are generated from the original by a language model. Check the original before relying on it.
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