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NVIDIA
Technology company that designs powerful computer chips used for video games, data centers, and artificial intelligence.
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Introducing CUDA Rust: Two Tracks for Writing GPU Kernels
NVIDIA’s CUDA Rust effort targets the GPU-kernel gap in Rust-based systems, where host code can be Rust but kernels often require another language. It presents two tracks: cuda-oxide compiles #[kernel] functions through Rust MIR, Pliron, and LLVM IR to PTX for SIMT programming, while cutile-rs expresses computations as tiles and JIT-compiles embedded ASTs through CUDA Tile IR. The SIMT example uses DisjointSlice, typed thread indices, and launch contracts to constrain per-thread output access and validate launch configuration; Tile leaves thread mapping and shared-memory management to its compiler. The post recommends starting with Tile because the compiler decides tile mapping per architecture, and using SIMT when explicit thread or memory control is needed. Both projects are early-stage, with cuda-oxide in early alpha and cutile-rs further along but still incomplete and subject to API changes.
Building a Memory-Driven Agent with NVIDIA NemoClaw
Enterprise agents need more than conversation history to connect decisions, obligations, people, and projects that change over time. Using NVIDIA NemoClaw, the example builds a memory-driven Chief of Staff around a human-readable self model in structured Markdown, a SQLite ledger for obligations and judgments, scheduled maintenance, bounded retrieval, and user correction with append-only auditing. Its architecture separates evidence, knowledge, and governed execution, while NVIDIA OpenShell sandboxes runtime access and keeps managed inference and MCP credentials outside the sandbox; memory can inform an action but cannot authorize it. In the supplied evaluation, the self model reached 90.9% overall accuracy versus 82.8% for an agentic RAG baseline, with larger gains on hard questions, changing facts, point-in-time reasoning, entity disambiguation, and multisource synthesis, but lower scores on corpus-faithful answers and single-hop lookup.
Frontier Reasoning Reaches the Edge: How to Deploy and Optimize Models on NVIDIA Jetson
Reasoning and agentic models have typically required data-center inference, creating network dependencies, higher costs, and potential data exposure for edge applications. The post explains how to choose between dense Qwen3.8-27B, which activates all 27 billion parameters, and mixture-of-experts Nemotron 3.5 Lightning, which has 30 billion total parameters but activates 3 billion per token. Deployment uses vLLM on Jetson with NVFP4 quantization and speculative decoding, where a draft model proposes tokens and the main model verifies them; the examples include DSpark for Nemotron and DFlash2 for Qwen. Reported tests show up to 6.28x decode-throughput speedup over BF16, while workload-specific throughput still varies. Validation with representative prompts is recommended before deployment, and custom quantization or speculator training is reserved for cases where accuracy or acceptance rates reveal a clear gap.
How to Carry User Identity Across Federated Kubernetes and AI Platforms
Federated data and AI platforms let users move among portals, datasets, notebooks, and assistants across clusters, but single sign-on alone does not carry trusted identity across control-plane and data-plane boundaries. The post presents a central identity gateway that owns platform sessions through OIDC, a shared session store, stateless data-plane gateways, and an identity-validation API. Regional gateways validate sessions through /gateway/userinfo, enforce local policy, and inject standardized identity headers instead of forwarding raw tokens or independently managing refresh and logout. This separates session ownership from request enforcement, supports consistent logout, and lets assistants pass delegated user identity to backend tools without broad service credentials. At NVIDIA, the approach reduced repeated login events by 55% across internal developer platforms spanning Kubernetes clusters in AWS and OCI, while establishing a foundation for unified platform shells and AI assistants.
NVIDIA PAIR Virtual Inference Router Expands Available Compute on Your Local Network
NVIDIA Personal AI Router (PAIR) addresses the GPU bottleneck created when multi-agent workflows and concurrent local sessions generate many independent inference requests. It acts as a virtual inference router rather than an inference engine, proxying compatible Ollama and LM Studio interfaces, discovering and securely pairing local systems, and scheduling each request onto one eligible node based on readiness, engine state, model availability, workload, and GPU utilization. The agent keeps one familiar connection, while PAIR streams responses back and exposes placement through Jobs and metrics views; it does not merge GPUs, pool VRAM, or split a single request across machines. In an unofficial Hermes five-subagent demonstration, a three-device cluster averaged 8 minutes 48 seconds versus 18 minutes on one RTX Spark laptop, with results explicitly dependent on configuration and workload.
The Modern CUDA Toolbox in Practice: A Step-by-Step Optimization Walkthrough
An image-processing pipeline serves as the test case for a modern CUDA toolbox, starting with RGB-to-grayscale conversion, 32-by-32 tile median computation, and host/device transfers. It advances through six incremental changes: adopting CCCL and Compute Sanitizer for indexing bugs, adding NVTX for Nsight Systems benchmarks, replacing hand-rolled work with CUB algorithms, using pooled device containers and pinned host containers, and assigning each image its own stream with asynchronous copies. The implementation uses cuda::stream, cuda::copy_bytes, cuda::device_buffer, and CUB calls on per-thread streams, allowing kernels and transfers to overlap instead of executing sequentially on the default stream. The reported total duration falls from 6.8 seconds to about 23 milliseconds for three images, a roughly 300x improvement, while the post characterizes the code as safer and easier to maintain without low-level optimizations.
Co-Designing AI Models Using Speculative Decoding for Faster LLM Inference
Speculative decoding accelerates large language model inference by having a smaller draft model propose multiple tokens and a target model verify them in parallel, preserving the standard output sequence under its acceptance criteria. It reduces decoding iterations and increases target-model arithmetic intensity, but speedup depends on acceptance length, verification time, draft latency, batch size, and hardware behavior. For attention-heavy workloads, the recommended starting point is D = 128/G - 1, where G is query heads per KV head; larger D values should align G × (1 + D) with 128-token kernel tiles. The remaining guidance covers compute-bound GEMMs, low-latency draft-cost tradeoffs, and choosing among external models, EAGLE-3, MTP, DFlash, DSpark, and suffix or n-gram methods; SPEED-Bench, TensorRT LLM, and NVIDIA/Model-Optimizer support measurement, training, and quantization workflows.
Building an Adaptive Agentic Cybersecurity System with NVIDIA Nemotron
NVIDIA and CrowdStrike describe an agentic cybersecurity system that links red-agent attack execution with blue-agent detection engineering in a continuous offense-defense testing loop. In an isolated environment modeled on NVIDIA accelerated computing infrastructure, Falcon sensors captured telemetry while Nemotron 3 Ultra orchestrated the defensive workflow and a customized Nemotron 3 Super generated or repaired detections. The harness grounded agents in sensor schemas and attack traces, then applied linting, replay, structured correction, and independent review before deployment. Backtesting raised mean detection of the recorded attack from 16.5% to 41.9% with the optimized open pipeline across independently seeded sessions. In live-fire tests, five of 11 open detections detected an unseen attack, three qualified as gold, and those three covered all eight attacks; the authors call the result a directional case study because it used one scenario family and limited benign traffic.
How to Size GPUs for AI Inference and TCO Without Overspending
GPU sizing for AI inference depends on use case, token patterns, latency targets, concurrency, cache hit rate, model choice and deployment strategy rather than raw hardware specifications alone. The post proposes a core-and-flex capacity model, combining baseline on-prem or reserved cloud capacity with elastic spot or on-demand GPUs for surges, launches and experiments. It also recommends matching GPU memory to prompt lengths and concurrency, while using quantization, pruning and distillation to reduce footprint and operating cost. A NeMo example prunes Qwen3-8B from 36 to 24 layers or narrows its dimensions toward a roughly 6B student before teacher-student distillation. In the illustrative run, width pruning reached lower final validation loss than depth pruning, 3.21 versus 3.60, while depth pruning converged faster.
Run NVIDIA BioNeMo NIM Microservices for Protein Structure Prediction in Claude Science
Claude Science is used with the NVIDIA BioNeMo Agent Toolkit and NVIDIA NIM microservices to investigate how the predicted Seh1 structure changes alone versus with proposed partner C1HCX1. The workflow retrieves UniProt sequences, generates unpaired and species-paired multiple-sequence alignments with MSA Search, and sends those inputs to OpenFold3 and Boltz-2 for independent monomer and heteromer predictions. Using MSA input, heteromer iPTM reached 0.85 for OpenFold3 and 0.82 for Boltz-2, versus 0.14 and 0.19 without it; five-sample runs had standard deviations no greater than 0.006. Both models placed partner β-strands at Seh1’s WD40 propeller closure, while core Cα-RMSD remained 0.68 Å and 0.65 Å, respectively, but the predicted interaction remains experimentally unverified.
Scale AV Perception Across Vehicle Platforms with NVIDIA Omniverse NuRec
Autonomous-driving perception changes when the same software moves across carlines because sensor placement, calibration, fields of view, occlusions, geometry, timing, and coverage change. The post presents NVIDIA Omniverse NuRec as a way to adapt a stack before a complete target-carline dataset exists, while retaining real-world data for grounding and validation. NuRec reconstructs recorded drives with 3D Gaussian splatting, renders novel views through a target rig with configurable camera models and calibration, and preserves trajectories, annotations, and map data for label adaptation. The workflow pairs a reconstructed scene with a rig, renders target views, refines frames with NVIDIA Harmonizer, and trains a perception model on the output. It also documents containerized rendering and auxiliary-data generation, including semantic masks, metric depth, and ego-vehicle masks, while noting that views outside observed coverage may be lower quality.
Deploy an Open Model from Checkpoint to Inference in Two Commands with NVIDIA TensorRT Model Connect
Deploying open models into native applications can require model-specific conversion, preprocessing, post-processing, and runtime code. NVIDIA TensorRT Model Connect addresses this with reference implementations that turn a Hugging Face model ID or local checkpoint into a deployment bundle containing TensorRT engines and runtime assets, then load it from a native C++ application. Its semantic API exposes task-level inputs and outputs, while its module-level API provides named tensors and individual TensorRT components; TVM FFI can connect custom GPU kernels to targeted pipeline stages. Python is used during preparation, but production inference does not require PyTorch or a Python interpreter. The project uses AI-assisted development, human review, nightly releases, and automated validation, and the post states that supported, validated workloads can deliver faster inference than torch.compile.
NVIDIA NVLink Fusion Brings NVHBM to Next-Generation AI Infrastructure
AI factories need custom XPUs to handle larger models and complex reasoning workloads, but scaling them requires HBM bandwidth, package and silicon area, power efficiency, supply-chain resilience, and rack-scale integration. NVIDIA NVLink Fusion addresses this by connecting custom XPUs and CPUs to NVIDIA’s AI infrastructure platform, using its scale-up and scale-out stack, ecosystem, and MGX rack-scale architecture. Its package-level NVHBM custom HBM base die, designed and validated with leading memory vendors, provides up to 30% more bandwidth and 15% lower HBM power usage than standard HBM4e, while enabling up to 25% more compute die area. The combined NVLink Fusion and NVHBM design is described as delivering a 30% overall end-to-end performance increase per XPU and simplifying integration into heterogeneous, rack-scale deployments.
How to Train a Cross-Embodiment Robot Navigation Policy with AI Agents
The tutorial presents an agent-driven workflow for adapting robot navigation across embodiments and scenes, addressing the repeated cost of collecting data, preparing simulation assets, training, diagnosing, and evaluating each robot-scene pair. Using Boston Dynamics Spot, it applies COMPASS to a built-in warehouse and a SAGE-10K scene, with NVIDIA Omniverse NuRec described as an option for captured environments. COMPASS reuses the pretrained NVIDIA X-Mobility navigation policy and trains a residual reinforcement-learning specialist that corrects base actions for a selected robot and environment; specialists can later be distilled into a shared policy. Repository skills guide dependency checks, asset preparation, smoke testing, training, checkpoint comparison, and packaging, while human gates control scene acceptance, smoke-test continuation, and checkpoint promotion. Runtime integration converts camera images, goals or routes, and speed from odometry into velocity commands, with cuVSLAM available separately when compatible odometry and transforms are unavailable.
Experiment with Qwen3.8-Flash-Next on NVIDIA GB300 NVL72 for Agentic Coding
Alibaba released the model weights for Qwen3.8-Flash-Next as a preview of the upcoming Qwen4 architecture, enabling developers to experiment with a multimodal mixture-of-experts model with a 125B-parameter main model, 51B N-gram embeddings, and 6B parameters activated per token. It supports a native 262,144-token context window, extensible to 1M tokens with YaRN. To reduce long-context attention compute and KV-cache growth, its hybrid design uses Gated DeltaNet in three of every four layers and Qwen Sparse Attention in the remaining layer, where micro-block importance guides retrieval. On NVIDIA GB300 NVL72, it delivers more than 16K tokens per second per GPU and more than 200 tokens per second per user; QSA achieved up to 7.6x prefill and 4.9x decoding speedups versus full attention. Fine-tuning is available through NVIDIA NeMo AutoModel with SFT or LoRA, and reinforcement learning through NVIDIA NeMo RL.
Restore LLM Inference Capacity in Seconds with Shadow Engine Recovery in NVIDIA Dynamo
LLM engine process failures typically trigger cold restarts that reload weights into HBM, compile kernels, and recapture CUDA graphs, leaving surviving workers to absorb displaced traffic for minutes. Shadow engine recovery, a preview feature in NVIDIA Dynamo, keeps a fully initialized standby on the same GPUs as the active engine. GPU Memory Service (GMS) preserves one physical weight copy across engine processes, while the parked shadow precomputes its CUDA context, graphs, communicators, and mappings but defers KV cache materialization. In a GLM-5.2 test, the shadow resumed service in 7.3 seconds after a worker failure, compared with 283 seconds for a cold restart, reducing post-fault p50 TTFT from 23,815 ms to 1,311 ms and improving decode rate from 12 to 46 tok/s/user. The preview does not cover hardware, node, or multi-node failures and currently starts promoted shadows with empty KV caches.
CUDA Python 1.0: Stable APIs, One Foundation, Full Platform Access
CUDA Python 1.0, released with CUDA 13.3, presents Python as a supported way to access the full NVIDIA CUDA platform. It addresses a fragmented ecosystem in which libraries used separate binding layers, complicating shared GPU memory, streams, and resource ownership, and forcing developers toward either CUDA C++ extensions or higher-level libraries. The release combines independently versioned components, including cuda.core, cuda.compute, cuda.bindings, cuda-pathfinder, and nvmath-python, with semantic-versioning and deprecation commitments. cuda.core supplies common Python objects for devices, streams, and buffers, allowing NVIDIA and external libraries to compose on shared resources, while cuda.bindings offers 1:1 CUDA C API coverage. The stack spans runtime services, tuned CUDA libraries, communication tools, and kernel-authoring systems, although some newer kernel languages remain experimental and outside the 1.0 guarantees.
Giga-Scale AI and the Ethernet Evolution: How Spectrum-X Ethernet Rewrites the Rules
Generative AI training across hundreds of thousands of GPUs makes the scale-out network a first-order performance bottleneck, because synchronized collectives expose weaknesses in conventional Ethernet. Static ECMP, packet loss controls such as PFC, and slowly tuned congestion control can create stragglers, head-of-line blocking, latency spikes, and multi-tenant interference. Spectrum-X Ethernet addresses these conditions with hardware-accelerated adaptive per-packet routing, targeted ECN- and RTT-based congestion control, and a SuperNIC Plane Load Balancer that distributes traffic across independent network planes. Spectrum-X Multiplane uses shallow two-tier fat trees and host-edge optical devices to provide path diversity while scaling a two-tier design to over 128,000 endpoints. In the cited tests, Spectrum-X sustained 98% of theoretical line rate across GPU pairs, held P99 tail latency to 8–9 microseconds under 75% load, recovered from a link flap in 2.68 milliseconds, and limited bandwidth loss under 10% fabric failure to 11%.
NVIDIA Vera Rubin and Blackwell Set a New Standard for Agentic AI Performance per Watt
Agentic AI inference has shifted from single-turn requests to long, stateful workflows that reason, invoke tools, coordinate subagents, and reuse growing context, increasing token and power demands. The post presents SemiAnalysis AgentX, an InferenceX benchmark that replays prerecorded Claude Code sessions turn by turn, preserving context, input/output lengths, reasoning time, tool-call latency, and KV-cache pressure while varying concurrency. It evaluates tokens per megawatt alongside E2E normalized interactivity, standard interactivity, E2E latency, and TTFT; NVIDIA-measured Vera Rubin NVL72 results, pending SemiAnalysis review, show up to 30x higher throughput per megawatt than GB300 NVL72 at 160 tokens per second per user. GB300 also delivers up to 15x H200 throughput per megawatt, up to 10x lower cost per million tokens, and roughly 80x higher throughput on Kimi K3 2.8T, supported by MoE runtimes, communication overlap, Dynamo, and NVLink.
Maximizing AI Factory Performance per Watt with NVIDIA DSX MaxLPS
Power-constrained AI factories measure efficiency by AI output per watt, because facility overhead, rack losses, and operational inefficiency reduce the power available to compute. In an illustrative 100 MW budget, 60% reaches AI load, while static rack provisioning can strand headroom that another rack could use. NVIDIA DSX MaxLPS addresses this with dynamic power allocation, workload-profile power optimization, and 45° C thermal and site design, including warm-water liquid cooling. Its Dynamic Power Software, currently in Developer Preview, models topology from utility to GPUs and reallocates unused capacity within policy-defined budgets, with optional DSX Exchange integration. For Vera Rubin NVL72, NVIDIA projects up to 40% more Rubin GPU capacity within the same power budget, while validation compares unmanaged and managed runs using throughput, latency, errors, power, utilization, and compliance.
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